The invention relates to the field of static random access memories (SRAM) working over very broad range of supply voltage values, and for example used in portable electronic devices such as smart phones, digital tablets, laptops, etc.
For so-called high-performance and low-consumption modern portable applications, it is interesting to use integrated circuits designed to work over a very broad range of supply voltage values so as to be able to dynamically adapt the value of the supply voltage of the circuits as a function of their use, and thus to optimize the energy performance of those circuits and reduce their electricity consumption so as to save on battery time.
In digital integrated circuits, the possible values of the supply voltage of those circuits are generally limited by the memories of those circuits. Indeed, the variability of the CMOS transistors present in the memories prevents them from working at a supply voltage as low as that of the elements forming the logic of the integrated circuits because the architecture of the memory leads to a deterioration of their performance greater than for the elements forming the logic when the supply voltage is reduced. For example, by reducing the supply voltage, the access time of the SRAM memories increases more quickly than the propagation time of the logic circuits.
In integrated circuits, several types of memories are used. The closer the memory is to the computing unit, the closer its performance and operating conditions will be to those of the computing unit. Thus, the cache memory L1, which is glued to the computing unit, is generally designed from SRAM memory cells with 6 or 8 transistors (called 6T or 8T). These memory cells are developed to achieve a better compromise of the following criteria:                good stability of the stored information,        ease of writing,        a maximum read current (ICELL) to have good performance,        a reasonable cell size to have a high integration density associated with low deteriorations of the performance caused by metallization of the cell, and        a minimal retention current (IOFF) to minimize the consumed static power.        
The dispersions obtained with the deca-nanometric CMOS technologies of 28 nm and less prevent, however, a guarantee of these criteria with a high performance (of approximately 5 to 6 sigmas, or an error rate of approximately 10−9). At a low voltage, these conditions are even more difficult to achieve.
In parallel to these considerations, reducing the dimensions of electronic components requires using new technologies to produce these integrated circuits. Thus, for technological nodes of 28 nm and below, the FDSOI (Fully Depleted Silicon-On-Insulator) technology makes it possible to improve the electrostatic control and dispersions of MOS transistors. Furthermore, the threshold voltage of an FDSOI transistor can be adjusted by doping and polarization on the rear face of the transistor. N- or P-wells can be used, both for NMOS and PMOS transistors. This FDSOI technology offers a means to improve the performance of memory circuits without additional design efforts.
The document “6T SRAM design for Wide Voltage Range in 28 nm FDSOI” by O. Thomas et al., SOI Conference (SOI), 2012 IEEE International, 1-4 Oct. 2012, Napa, Calif., pages 1-2, describes a 6T memory cell made using 28 nm FDSOI technology whereof the mono-P-Well architecture (only one P-well shared by all six transistors of the memory cell) makes it possible to decrease the supply voltage value of the transistors of the cell, in particular by improving writing. However, the write optimization and read optimization remain dependent on one another. Yet the reduction in the supply voltage causes a decrease in the possible read speed.
The document “An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment” by Y. Morita et al., VLSI Circuits, 2007 IEEE Symposium on, 14-16 Jun. 2007, Kyoto, JP, pages 256-257, describes an 8T memory cell that includes, relative to a 6T memory cell, two additional transistors forming the read port of the cell. This read port makes it possible to decorrelate the reading from the writing done in the cell because during reading, the two access transistors used for writing in the cell remain in the blocked state. As for a 6T memory cell, this alternative may be improved using FDSOI technology. However, a drop in the supply voltage of the transistors of the cell nevertheless causes a drop in the read speed that can be achieved by such a memory cell.
Furthermore, for high-performance applications, whether the memory cells include 6 or 8 transistors, the performance of the memory circuits is affected by timing faults, or synchronization faults, in read and write. A read timing fault is due to a read current of the cell that is too low to discharge a bit-line quickly enough in the allotted access time. A write timing fault is due to the excessively long switching time of the memory cell to store a bit correctly. The read timing faults can also be created by an excessively long write time because in that case, the completion of logic level “1”, i.e., the transition of the potential from the node with logic level “0” toward logic level “1” during writing, is not complete (completion being able to end during the following cycle), which limits the read current during the following cycle if it involves reading because the potential in the node is then lower than the potential correspondent to logic level “1”. Yet the number of cells showing such a malfunction increases when the supply voltage of the memory cells is reduced.
In the matrix of memory cells, redundancy solutions for a column or row of cells have been proposed to offset these problems, as for example described in document “Row/Column Redundancy to Reduce SRAM Leakage in Presence of Random Within-Die Delay Variation” by M. Goudarzi et al., Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on, 11-13 Aug. 2008, Bangalore, pages 93-98. These redundancies are used to replace the columns or rows of nonfunctional memory cells, i.e., the columns or rows of cells where one or more cells create read and/or write timing faults. The possible number of redundant columns or rows nevertheless remains limited due to the fact that a certain density of the matrix must nevertheless be kept. Furthermore, this solution requires reprogramming the access circuits to the matrix.
There are also solutions based on error correction codes (ECC). They associate additional bits with the word that makes it possible to detect and correct any errors. The programming of the additional bits is done through an encoding logic and verification by a decoding logic. ECC's are very effective to respond to “software” errors (assumed to be small in quantity), but are not suitable for low-voltage applications where the error rate increases very quickly.
These read and/or write timing fault problems created by a drop in the supply voltage are also found for SRAM memory cells comprising transistors other than CMOS FDSOI transistors, such as TFET transistors as described in document “A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications” by J. Singh et al., Proceedings of 15th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 181-186, January 2010.